The present invention generally relates to a scan converter control circuit having memories, and more particularly to a circuit for controlling a scan converter directed to reducing the bit rate of an image signal. Further, the present invention is concerned with an address generator which generates a zigzag address supplied to memories of the scan converter.
As is well known, an image signal has a wide frequency range. In order to transmit such an image signal in digital form, it is necessary to reduce the bit rate of the image signal. For this requirement, a bandwidth compression coding is proposed which utilizes the correlation between the spatial axis and the time axis.
The power of an image signal concentrates on the low frequency components thereof. From this point of view, the bandwidth of the image signal is compressed by an orthogonal transform coding in which the image data is converted into frequency components. Examples of the orthogonal transform coding are a discrete cosine transform (DCT) coding, Hadamard transform (H) coding and Fourier transform (FT) coding.
In the discrete cosine transform, output data Y is obtained by the formula, Y=CXC.sup.t, where X is input data, C is a predetermined square matrix based on the transform type and C.sup.t is the transposed matrix of the square matrix C. In order to realize the above-mentioned formula by using hardware, the following procedures are required. Matrix data (8.times.8 pixel data) must be rearranged on the input and output sides of an operation unit. Matrix data which is transferred in synchronism with a data input clock must be input to the operation unit in synchronism with an operation clock. Matrix data which is output from the operation unit in synchronism with the operation clock must be output in synchronism with a data output clock.
Referring to FIG. 1, there is illustrated a DCT coding circuit which implements the above-mentioned procedures required to realize the aforementioned formula by hardware. Input data applied to the DCT coding circuit is sent to an operation unit 82 via a scan converter 81. The operation unit 82 executes a predetermined operation procedure using coefficient data read out from a memory 83. The calculation results output by the operation unit 82 are sent to an external circuit of the next stage via a scan converter 84.
Each of the scan converters 81 and 84 has two memory planes (areas) and a controller (software). The controller alternatively switches the two memory planes and controls read and write addresses supplied to the two memory planes.
FIG. 2 is a diagram illustrating a memory plane switching operation, a write operation and a read operation. One of the two memory planes is input to 64 pixel data DT-IN in synchronism with a data input signal XDIN (FIG. 2(A)). The 64 data DT-IN are written into the memory plane in a writing order shown in FIG. 2(B), that is, a receiving sequence in a vertical scan. After the 64 data DT-IN are completely written into the memory plane, the 64 data DT-IN are read out from the plane in a read order shown in FIG. 2(C), that is, an output order in a zigzag scan. The readout data are indicated by DT-OUT in FIG. 2(A). On the other hand, 64 data are input to the other memory plane in synchronism with the next data input signal XDIN. Then, the write and read operations are carried out in the same way as described above. With the above-mentioned arrangement, it becomes possible to rearrange successive input data.
The procedure for alternately writing input data into the two memory planes of each of the scan converters 81 and 84 is alternately switched in accordance with the data input signal XDIN. The procedure for reading out data from the memory planes is carried out subsequently after the writing of input data is completed. In this manner, the memory plane switching procedure is independently carried out for each of the two memory planes. Conventionally, the memory plane switching procedure is realized by software (program). In this case, a huge number of steps are necessary to implement the memory plane switching procedure. Thus, it is very difficult to execute the memory plane switching procedure in real time. As a result, it is very difficult to process consecutive image data in real time.